1. Field of the Invention
The present invention relates to a delay-locked loop device, and more particularly, a delay-locked loop device capable of anti-false-locking and increasing the operating range with a lock detector.
2. Description of the Prior Art
Digital integrated circuits have been highly developed. Personal computers, mobile phones, digital watches, and calculators, for example, are applications of digital integrated circuits. With high-speed, microminiaturized, and multi-function developments, a complex digital integrated circuit often includes a plurality of units. The units delay a reference timer with different degrees, so a delay-locked loop (DLL) device is need for maintaining synchronization of the digital integrated circuit.
Please refer to FIG. 1, which illustrates a schematic diagram of a prior art DLL device 10. The DLL device 10 includes a phase detector 12, a charge pump 14, a loop filter 16, a voltage control delay circuit 18, and a reference-phase generator 20. The reference-phase generator 20 generates a reference phase Fr for the voltage control delay circuit 18 and the phase detector 12. The voltage control delay circuit 18 includes a plurality of delay units 22 each controlled by a voltage Vc provided by the loop filter 16 to delay the reference phase Fr. The voltage control delay circuit 18 delays the reference phase Fr according to the voltage Vc provided by the loop filter 16, and outputs a delayed phase Fd to the phase detector 12 from the last-stage delay unit 22 of the voltage control delay circuit 18. The phase detector 12 generates a phase difference between the reference phase Fr and the delayed phase Fd, then determines whether the voltage control delay circuit 18 delays the reference phase Fr with a predetermined value, and controls the charge pump 14 to increase or decrease output charges for the loop filter 16 according to the phase difference. The loop filter 16 transforms the charges provided by the charge pump 14 to the voltage Vc for controlling the delay amount (degree) of the delayed phase Fd corresponding to the reference phase Fr. That is, each delay unit 22 of the voltage control delay circuit 18 delays the reference phase Fr with an amount, and the last delay unit 22 outputs the delayed phase Fd to the phase detector 12, which determines the phase difference between the reference phase Fr and the delayed phase. For example, if one cycle delay is needed, but the phase difference between the reference phase Fr and the delayed phase Fd is greater than a cycle (or 360°), the phase detector 12 triggers the charge pump 14 to increase output charges for the loop filter 16, so as to output a larger voltage Vc to each delay unit 22 of the voltage control delay circuit 18. The larger voltage Vc causes each delay unit 22 decreasing the delay amount, so the phase difference between the delayed phase Fd and the reference phase Fr decreases. On the other hand, in this case, if the phase difference between the reference phase Fr and the delayed phase Fd is smaller than a cycle, the phase detector 12 triggers the charge pump 14 to decrease output charges for the loop filter 16, causing a smaller voltage Vc and a larger delay amount of each delay unit 22 accordingly, so the phase difference between the delayed phase Fd and the reference phase Fr increases. Therefore, with a close loop 24 shown in FIG. 1, the DLL device 10 outputs the delayed phase Fd from the last delay unit 22 of the voltage control delay circuit 18 to a system for synchronization.
However, the operations of the prior art DLL device 10 are limited by effects of harmonic lock and stuck lock. Please refer to FIG. 2, which illustrates a waveform diagram of a lock range of the DLL device 10. In FIG. 2, a cycle Tr represents a cycle of the reference phase Fr generated by the reference-phase generator 20 in FIG. 1; durations Tmax and Tmin represent the maximum and the minimum delay ranges of the delayed phase Fd; a waveform Wr represents a waveform of the reference phase Fr; waveforms Wd,max and Wd,min represent waveforms of the delayed phase Fd in the maximum and the minimum delays. What is so-called “harmonic lock” is that because the phase detector 12 of the DLL device 10 only detects the phase difference between the delayed phase Fd and the reference phase Fr, wrong decisions of the phase detector 12 occur when a delayed phase generated by the voltage control delay circuit 18 is integer times the phase difference between the needed delayed phase Fd and the reference phase Fr. For example, when a phase Fd delaying 2Tr is needed, the phase detector 12 of the DLL device 10 sets the phase difference between the delayed phase Fd and the reference phase Fr being 720°, and controls the charge pump 14 to increase or decrease charges for the loop filter 16. However, when the phase difference between the delayed phase Fd and the reference phase Fr is 1440° (that is, the phase Fd delays 4Tr), the phase detector 12 determines that the DLL device 10 has locked accurately (for 1440°=2×720°). In order to prevent the effect of harmonic lock, the maximum lock range of the DLL device 10 is limited to Tmax. Moreover, the process of reaching lock also limits the minimum lock range of the DLL device 10 as Tmin. In short, because of the effects of harmonic lock and stuck lock, the lock ranges of the prior art DLL device 10 should be Tr<Tmax<1.5Tr and 0.5Tr<Tmin<Tr. Nevertheless, the limitations of the lock ranges cannot conform to some applications, and may cause false lock.
To improve the above-mentioned problems, the prior art uses a lock detector. Please refer to FIG. 3, which illustrates a schematic diagram of a prior art DLL device 30. The DLL device 30 includes a phase detector 32, a charge pump 34, a loop filter 36, a voltage control delay circuit 38, a reference-phase generator 40, and a lock detector 46. The reference-phase generator 40 generates a reference phase Fref for the voltage control delay circuit 38 and the phase detector 32. The voltage control delay circuit 38 includes a plurality of delay units 42 each controlled by a voltage Vct provided by the loop filter 36 to delay the reference phase Fref. The voltage control delay circuit 38 delays the reference phase Fref according to the voltage Vct provided by the loop filter 36, and outputs a delayed phase Fdl to the phase detector 32 from the last-stage delay unit 42 of the voltage control delay circuit 38. The lock detector 46 outputs a lock indication signal Sp to the phase detector 32 according to the reference phase Fref and each phase of the delay units 42 of the voltage control delay circuit 38. The lock indication signal Sp includes an under, a right, and an over signals for indicating the phase detector 32 whether the delayed phase Fdl is under, right, or over delay. After receiving the lock indication signal Sp, the phase detector 32 determines whether the delayed phase Fdl delays in a specific range (for avoiding the harmonic lock and the stuck lock), and controls the delayed phase Fdl with a close loop according to a phase difference between the delayed phase Fdl and the reference phase Fref. As to the configuration of the lock detector 46, please refer to FIG. 4, which illustrates a schematic diagram of the lock detector 46 of the prior art DLL device 30 in FIG. 3. The lock detector 46 includes a state machine 48 and a serial shift register set. The serial shift register set 50 includes a plurality of D flip-flops 52. Each of the D flip-flops 52 corresponds to each delay unit 42 of the voltage control delay circuit 38, and is triggered by rising edges of the reference phase Fref to sample output signals (CK1˜CKN) of the delay units 42 of the voltage control delay circuit 38, so as to output a sequence of signals Q1, Q2 to Qn for the state machine 48. The state machine 48 generates a truth table according to the sequence of the signals Q1 to Qn, and outputs the lock indication signal Sp to the phase detector 32. For example, if the voltage control delay circuit 38 includes four delay units 42, the lock detector 46 includes four corresponding D flip-flops 52, and a truth table shown in FIG. 5 is obtained according to a predetermined delay amount (such as one cycle). In FIG. 5, a row L1 represents that the output signals Q1 to Q4 generated by sampling the delay units 42 with the rising edges of the reference phase Fref delaying one cycle are 0. That is, the signals sampled by the rising edges of the reference phase Fref are low level, so the delayed phase Fdl outputted from the last delay unit 42 delays the reference phase Fref with a delay amount smaller than the predetermined delay amount (one cycle). As a result, the under signal of the lock indication signal Sp is set to be 1, representing that the delay amount between the delayed phase Fdl and the reference phase Fref is under (smaller than) the predetermined delay amount (one cycle), so as to indicate the phase detector 32 not to lock the false phase and to control the delayed phase Fdl by adjusting output charges for the charge pump 34 accordingly. By the same token, rows L2 to L4 in FIG. 5 represent that the delay amount between the delayed phase Fdl and the reference phase Fref almost equals the predetermined delay amount, and the right signal of the lock indication signal Sp is set to be 1. Therefore, the phase detector 32 determines that the delay amount of the delayed phase Fdl is in an right range, and controls the delayed phase Fdl with a close loop 44 for maintaining the right delay lock according to the phase difference between the delayed phase Fdl and the reference phase Fref. Moreover, in FIG. 5, rows L5 to L7 represent that the delay amount between the delayed phase Fdl and the reference phase Fref is over the predetermined delay amount (one cycle), so that the over signal of the lock indication signal Sp is set to be 1 for indicating the phase detector 32 not to lock the false phase and to control the delayed phase Fdl by adjusting output charges for the charge pump 34 accordingly.
Therefore, using the lock detector 46, the DLL device 30 detects every delay unit 42 of the voltage control delay circuit 38 for generating a truth table, and indicates the phase detector 32 not to lock false phases according to the truth table, avoiding harmonic lock and stuck lock. However, in high-precision applications, the precise delayed phase Fdl is needed. As a result, the DLL device 30 increases the delay units 42 of the voltage control delay circuit 38, and the corresponding D flip-flop 52 of the serial shift register set 50, causing a huge truth table in the state machine 48 occupying more system resources. Moreover, each unit (or block) in a system uses the DLL device for synchronization, so in the high-precision applications, the DLL devices cost a lot of resources further. Besides, when the reference-phase generator affected by noises generates the reference phase Fref having jitters, or having an asymmetric duty cycle (that is, the duty cycle differ from 50%), a false lock occurs in the DLL device 30. For example, please refer to FIG. 6 (also FIG. 5), which illustrates a waveform diagram of the reference phase Fref and output signals of the delay units 42 when the voltage control delay circuit 38 in FIG. 4 includes four delay units 42 and the duty cycle of the reference phase Fref is 70%. In FIG. 6, a signal Wref is the waveform of the reference phase Fref, and signals Wck1 to Wck4 are waveforms of output signals of the first to the fourth delay units 42. If a one-cycle delay amount between the delayed phase Fdl and the reference phase Fref is needed, the phase detector 32 can delay the reference phase Fref with one cycle accurately when the output signals Q1 to Q4 generated by sampling the delay units 42 with the rising edges of the reference phase Fref delaying one cycle conform to the rows L2 to L4 of the truth table in FIG. 5. However, as shown in FIG. 6, when the duty cycle of the reference phase Fref is 70%, the output signal Wck4 of the fourth delay unit 42 does not delay with the needed one cycle in comparison with the signal Wref, but owing to the 70% duty cycle of the reference phase Fref, the output signal (or Q4) of sampling the fourth delay unit 42 with the rising edges of the reference phase Fref delaying one cycle is high level (or logic 1), meaning that the DLL device 30 is in the right delay lock according to the row L2 in FIG. 5. In short, when the duty cycle of the reference phase Fref is greater than 50%, error delays may occur in the prior art DLL device 30. By the same token, please refer to FIG. 7, which illustrates a waveform diagram as shown in FIG. 6, but the duty cyle of the reference phase Fref is 30%. Owing to the 30% duty cycle of the reference phase Fref, the situation in FIG. 7 conforms to the row LI in FIG. 5, or under lock, but actually, the DLL device 30 is in the right delay lock.
In summary, the prior art DLL device 10 cannot detect harmonic lock and stuck lock, and although the prior art DLL device 30 can detect them, the DLL device 30 costs a lot of system resources as the delay units 42 increase. Moreover, as shown in FIG. 5, the lock range of the DLL device 30 is between the rows L2 to L4 and is limited between 0.5 and 1.5 cycles of the reference phase Fref. Furthermore, the DLL device 30 can only operate with the 50% duty cycle of the reference phase. Therefore, the prior art DLL device costs system resources, but is incapable of achieving accurate delay locks, and the system may be unstable in synchronization when suffering noises or other affections.